﻿using System;
using System.Collections.Generic;
using System.Linq;
using System.Text;

namespace Tomasulo_Simulator
{
    class ReorderBufferEntry
    {

        Processor.Operation operation;
        int destination;
        int result;
        int predictedBranch;
        int correctBranch;
        bool ready;

        public Processor.Operation Instruction
        {
            get { return operation; }
            set { operation = value; }
        }
        public int Destination
        {
            get { return destination; }
            set { destination = value; }
        }
        public int Value
        {
            get { return result; }
            set { result = value; }
        }
        public bool Ready
        {
            get { return ready; }
            set { ready = value; }
        }

        public ReorderBufferEntry(Processor.Operation operation, int destination, int predictedBranch)
        {
            this.operation = operation;
            this.destination = destination;
            this.predictedBranch = predictedBranch;
            this.result = 0;
            this.ready = false;
        }

        public void Commit()
        {
            switch (operation)
            {
                case Processor.Operation.BEQ:
                case Processor.Operation.JMP:
                case Processor.Operation.RET:
                    if (correctBranch != predictedBranch)
                    {
                        Processor.processor.Flush();
                        // processor.InstructionBuffer.PC = result;
                    }
                    break;
                case Processor.Operation.JALR:
                    Processor.processor.Regs[destination] = result;
                    if (correctBranch != predictedBranch)
                    {
                        Processor.processor.Flush();
                        // processor.InstructionBuffer.PC = result;
                    }
                    break;
                case Processor.Operation.SW:
                    ///////////////////////////////memory.store(result, destination);
                    break;
                default:
                    Processor.processor.Regs[destination] = result;
                    break;
            }
            ////////////registerstat[d].busy = no
        }
    }
}
